This invention relates to data communication systems, and more particularly, to a method and mechanism for processing frame data read from a memory for transmission from various ports of a communication switch.
A multiport communication switch may be provided in a data communication network to enable data communication between multiple network stations connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received data packets, e.g., frame data, to appropriate destinations. Based on frame headers, a frame forwarding arrangement selectively transfers received frame data (packet data) to a destination station.
Data packets received at a receive port of the communication switch are transferred to an external memory and subsequently retrieved and placed in a transmit queue for transmission from a respective transmit port of the switch. The length of the frame data read from the external memory is sometimes changed prior to writing to the transmit queue. Thus, there is a need to provide a method and mechanism for asserting a control signal indicating when frame data has been read from the external memory and a control signal indicating when the frame data has been written to a respective transmit queue in order to accommodate for a difference between the number of slots required to read from the external memory and the number of slots required to write to the transmit FIFO which may result from changing the length of the frame data read from the external memory.
The invention provides a novel arrangement for denoting when frame data has been read from the external memory and when it has been written to the transmit queue to accommodate a difference between the number of slots required to read frame data from the external memory and the number of slots required to write to the transmit FIFO resulting from modifications to the length of the read frame data. The apparatus includes a multiport data communication system for switching data packets between ports and comprises a plurality of receive ports for receiving data packets, a memory storing the received data packets, a plurality of transmit ports each having a transmit queue, and logic circuitry. The logic circuitry controls reading of a data packet from memory, provides a signal indicating an end of reading the data packet from the memory, decides whether a length of the read data packet is to increase, decrease, or remain the same, controls writing the read data packet to a corresponding transmit queue in accordance with the decision, and provides a signal indicating an end of writing the data packet to the transmit queue.
The logic circuitry also determines a number of read operations necessary to read the data packet, corresponding to read address data, from the memory, counts each read operation, and provides the signal indicating an end of reading the data packet from the memory when the counted read operations is equal to the number of determined read operations. The logic circuitry also modifies the length of the read data packet by increasing the length by a predetermined length when it is decided that the length is to increase and by decreasing the length of the read data packet by the predetermined length when it is decided that the length is to decrease, determines a number of write operations necessary to write the read data packet to the transmit queue in accordance with the decision as to whether the length of the read data packet is to increase, decrease, or remain the same, counts each write operation, and provides the control signal indicating an end of writing the data packet to the transmit queue.
The invention provides also a novel method of processing data packets received by a communication system having a plurality of receive ports for receiving the data packets, a memory storing the received data packets, and a plurality of transmit ports each having a transmit queue, comprising reading the data packet from the memory, asserting a signal indicating an end of reading the data packet from the memory, deciding whether a length of the read data packet is to increase, decrease, or remain the same, writing the read data packet to a corresponding transmit queue in accordance with the decision, and asserting a signal indicating an end of writing the data packet to the transmit queue.
Asserting the signal indicating an end of reading the data packet from the memory includes determining a number of read operations necessary to read the data packet from the memory, counting each read operation, and asserting the signal indicating an end of reading the data packet from the memory when the counted read operations is equal to the number of determined read operations.
Asserting the signal indicating an end of writing the data packet to the transmit queue includes modifying the length of the read data packet by increasing the length by a predetermined length when it is decided that the length is to increase and decreasing the length of the read data packet by the predetermined length when it is decided that the length is to decrease, determining a number of write operations necessary to write the read data packet in accordance with the decision as to whether the length of the read data packet is to increase, decrease, or remain the same, counting each write operation, and asserting the signal indicating an end of writing the data packet to the transmit queue when the counted write operations is equal to the number of determined write operations.
Various objects and features of the present invention will become more readily apparent to hose skilled in the art from the following description of a specific embodiment thereof, especially hen taken in conjunction with the accompanying drawings.